1. Field of the Invention
The invention relates to a semiconductor memory device and more particularly relates to a programming method for a NAND-type flash memory.
2. Description of Related Art
A typical NAND type flash memory includes a memory array that is composed of a plurality of NAND strings. The NAND string includes a plurality of memory cells connected in series, and a bit line selection transistor and a source line selection transistor connected to two ends thereof. FIG. 1 is a circuit diagram illustrating a configuration of the NAND strings formed in the memory array. In a memory block, multiple NAND strings (referred to as “cell units (NU)” hereinafter) formed by connecting multiple memory cells in series are disposed in row and column directions. In the example as shown, the configuration of one cell unit (NU) includes 32 memory cells MCi (i=0, 1, . . . , 31) that are connected in series, and a bit line selection transistor TD and a source line selection transistor TS connected to two ends thereof. A drain of the bit line selection transistor TD is connected to one bit line BL corresponding thereto, and a source of the source line selection transistor TS is connected to a common source line SL. Control gates of the memory cells MCi are connected to a word line WLi. Gates of the bit line selection transistor TD and the source line selection transistor TS are respectively connected to selection gate lines SGD and SGS that extend parallel to the word line WLi.
Generally speaking, the memory cell includes a source/drain having an N-type diffusion region formed in a P-well, a tunneling oxide layer formed on a channel between the source/drain, a floating gate (a charge accumulation layer) formed on the tunneling oxide layer, and a control gate formed on the floating gate via a dielectric film. Generally, when no charge is accumulated in the floating gate, namely, data “1” is written, a threshold value is negative, and the memory cell is normally on. When charges are accumulated in the floating gate, namely, data “0” is written, the threshold value shifts toward a positive direction, and the memory cell is normally off.
FIG. 2 is a table showing an example of bias voltages that are applied in each operation of the flash memory. In a reading operation, a positive voltage is applied to the bit line; a voltage is applied to selected word lines and a read pass voltage (e.g. 4.5V) is applied to non-selected word lines; a positive voltage (e.g. 4.5V) is applied to the selection gate lines SGD and SGS to turn on the bit line selection transistor TD and the source line selection transistor TS; and 0V is applied to the common source line SL. Accordingly, page data of the selected word lines is read via the bit line, and whether the threshold value of the read cell is higher than the voltage applied to the selected word lines is detected.
In a programming (writing) operation, a high-voltage programming voltage Vprg (15V˜20V) is applied to the selected word lines; an intermediate potential (e.g. 10V) is applied to the non-selected word lines to turn on the bit line selection transistor TD and turn off the source line selection transistor TS; and a potential corresponding to data “0” or “1” is provided to the bit line BL. In an erasing operation, 0V is applied to the selected word lines in the block; a high voltage (e.g. 21V) is applied to the P-well; and electrons of the floating gate are extracted to a substrate to use the block as a unit for erasing data. Detailed descriptions about the NAND type flash memory may be found in Japanese patent publication No. 2011-253591.
Flash memory is required to have a certain degree of endurance (data rewriting times) or data holding characteristics. When FN (Fowler-Nordheim) tunneling current flows through the gate oxide layer, if a portion of the electrons are captured by the oxide layer and stored in the oxide layer, it is difficult for the FN tunneling current to flow through even though a voltage is applied to the control gate. Thus, the data rewriting times are limited. In addition, if the charges stored in the floating gate are released as time passes, the stored data will be lost. Therefore, it is more ideal to prevent deterioration of the characteristic of the insulating layer that surrounds the floating gate. The conventional programming method is to apply a high voltage to the control gate to render the substrate (P-well) 0V, and apply a high electric field to the tunneling oxide layer so as to inject electrons by a FN tunneling effect. However, applying high electric field to the oxide layer and reiteratively performing the programming and erasing operations may lower the reliability of the oxide layer.